Sample

Serial ATA (SATA) Verification IP

The Serial ATA (SATA 1, 2, 3) System Verification Component (SVC) is designed to help you thoroughly verify your design using both random and directed simulation. The SVC supports constrained randomization parameters throughout the layers to aid in coverage during verification. The SVC is environment language neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog)

Overall Features
  • Compliant to SATA Rev 2.6+ and SATA 3.0 specifications
  • Supports all SATA commands (PIO, DMA, LCQ, NCQ)
  • Can be used at any link speed including 6 Gb (SATA 3)
  • Support for interrupt agregation
  • OOB sequence generation and checking
  • Includes a digital SERDES model with receiver clock recovery
  • Checkers will verify protocol timing checks and functional accuracy at each layer.
  • Scalable for multiple instantiations in a test bench (for testing multi-port hosts)
  • Configurable pattern generation for random, directed or erroneous patterns
  • Includes transactor interfaces for directed testing
  • A variety of constrained randomized parameters to aid in coverage during randomized testing
Device and Host Transport Layer Features
  • Constrained randomization by FIS type for timing of request/response.
  • Constrained randomization for both TX and RX Dword pacing
  • Device model is reactive, and can respond with error conditions
  • Device model emulates a small LBA mode disk and keeps data state
  • Callbacks for use in directed test writing
Link Layer Features
  • Selectable as Host or Device BFM
  • Complete Link Layer state machine
  • Selectable Primitive CONT and fill substitution processing
  • Selectable data scrambling option
  • CRC checking and configurable delay for CRC check
  • Configurable Receive and Transmit fifo latencies
ATA System Exerciser Applications
  • Exercises Host and Device as a system unit - either the Host, Device or both may be a DUT.
  • Randomizes I/O transactions and checks results
  • Scoreboards LBAs and expected data
  • Application layer can be reused to drive Host DUT instead of Host SVC
  • Includes a BIST exerciser mode
  • Exercises Power Management modes
ENDEC and Phy Layer Layer Features
  • Disparity checking
  • Kcode & Dcode validity and alignment
  • 8b/10b Encode and Decode functions
  • Controls to inject bit errors
  • OOB sequence generation and checking
  • Digital SERDES model included
  • Callbacks for use in directed test writing

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