Sample

Serial SCSI / SAS Verification IP

The Serial SCSI (SAS) System Verification Component (SVC) is designed to help you thoroughly verify your design using both random and directed simulation. These are full function models, not just a Bus Functional Model. The SAS SVC supports constrained randomization parameters throughout the layers to aid in coverage during testing. The SVC is implemented to be environment language neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog).

Overall Features
  • Compliant to SAS 2 and 2.1 / SPL specifications
  • Initiator (Host) and Target models
  • Full Expander models, including SMP port
  • SCSI Application level exerciser for both unit and system level testing.
  • Optional STP support with ATA Application level exerciser (See SATA product page for details)
  • Scalable for multiple instantiations in a test bench (for testing multi-port hosts or devices
  • OOB sequence generation and checking
  • Supports speed negotiation, training sequences and multiplexing at any link speed
  • Checkers will verify protocol timing checks and functional accuracy at each layer.
  • Configurable pattern generation for random, directed or erroneous patterns
  • A variety of constrained randomized parameters to aid in coverage during randomized testing
  • Statistics reported at each level to help determine corner case coverage.
  • User call-backs and hooks for use in directed tests
SCSI Exerciser Application
  • Compliant to SCSI Architecture Model 3 (SAM-3)
  • Supports Single Level LUN addressing
  • Host Model Capabilities:
    • A single Initiator can communicate with multiple Targets.
    • Initiator can discover target information or have this step skipped and set with appropriate target information
    • Supports both auto-command generation and scripted command generation.
    • Scoreboard keeps track of written data to handle corner cases such as data overlay, aborted tasks, and read/write data ordering.
  • Comprehensive suite of controls that define the behavior of the commands/task management functions
  • Target Model Capabilities:
    • Target implements a block mode device
    • Target is multiple LUN capable
    • Capable of responding to discovery commands such as INQUIRY, REPORT_LUNS, etc
    • Supports several queuing attribute models
    • Statistics report indicating command execution details.
Transport Layer
  • Frame Level error detection
  • SAS Address Hashing
  • Tag allocation, lookup and checking
  • XFER_READY and Data offset checkers
  • Frame Level Statistics
  • Supports multiple outstanding IOs/exchanges
  • Randomization of behaviors stressing common pitfalls
  • Optional STP Transport support
  • Configurable as initiator / target based on device type
Port Layer
  • Any combination of Phys per Wide Port
  • Randomized/iterative selection of PHY
  • Multiple simultaneous connections
  • Configurable connection close policies
Link Layer Features
  • Full support of SSP Link Layer, Simple SMP layer.
  • Optional STP Link support
  • SAS SPL Power Management support
  • All primitive sequence types supported
  • Reserved Primitive substitution
  • Idle generator (scrambled data words)
  • Configurable / randomized ALIGN/NOTIFY
  • Elasticity Buffer
  • Configurable SAS Address
  • Configurable timeouts
PHY Layer Features
  • SERDES model with digital receiver clock recovery
  • OOB sequence generation and checking
  • Speed negotiation - SNW-1,2 and SNW-3 - 1.5 to 6Gb
  • Support for Phy Multiplexing
  • Configurable Spread Spectrum Clocking (SSC) generation
  • SAS SPL Power Management support
  • Kcode and Dcode Checking
  • 8b/10b Encode and Decode functions with disparity checking
  • Controls to inject bit errors
  • Controls for Dword/Primitive override
  • Configurable timeouts

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