Serial SCSI (SAS 1 & 2)
Verification IP

The Serial SCSI (SAS) System Verification Component (SVC) is designed to help you thoroughly verify your design using both random and directed simulation. These are full function models, not just a Bus Functional Model. The SAS SVC supports constrained randomization parameters throughout the layers to aid in coverage during testing. The SVC is implemented to be environment language neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog).
 
Simply the most advanced and mature SAS Verification IP product on the market.
 
Overall Features:
 
Compliant with SAS-2r11 and SAS-1r10 specifications
 
OOB sequence generation and checking
 
Supports SNW-1,2,3 speed negotiation, training sequences and multiplexing
 
Can be used at any link speed including 6Gb, 3Gb, and 1.5Gb
 
Initiator (Host) and Target models
 
Full Expander models, including SMP port and optional STP bridges
 
SCSI Application level exerciser for both unit and system level testing.
 
Optional STP support with ATA Application level exerciser (See SATA product page for details)
 
Scalable for multiple instantiations in a test bench (for testing multi-port hosts or devices)
 
Checkers will verify protocol timing checks and functional accuracy at each layer.
 
Configurable pattern generation for random, directed or erroneous patterns
 
A variety of constrained randomized parameters to aid in coverage during randomized testing
 
Statistics reported at each level to help determine corner case coverage.
 
User call-backs and hooks for use in directed tests
 
SCSI Exerciser Application
 
Compliant to SCSI Architecture Model 3 (SAM-3)
 
Supports Single Level LUN addressing
 
Comprehensive suite of SVC settings that define the behavior and parameters of the commands/task management functions executed by the initiator.
     
 
Host Model Capabilities:
   
A single Initiator can communicate with multiple Targets.
Initiator can discover target information or have this step skipped and set with appropriate target information
Supports both auto-command generation and scripted command generation.
Scoreboard keeps track of written data to handle corner cases such as data overlay, aborted tasks, and read/write data ordering.
 
 
Target Model Capabilities:
   
Target implements a block mode device
Target is multiple LUN capable
Capable of responding to discovery commands such as INQUIRY, REPORT_LUNS, etc
Supports several queuing attribute models
Statistics report indicating command execution details.
 
 
Transport Layer:
 
Frame Level error detection
 
SAS Address Hashing
 
Tag allocation, lookup and checking
 
XFER_READY and Data offset checkers
 
Frame Level Statistics
 
SAM-3 standard SCSI Interface
 
Supports multiple outstanding IOs/exchanges
 
Randomization of behaviors stressing common pitfalls
 
Optional STP Transport support
 
Link Layer Features
 
Full support of SSP Link Layer, Simple SMP layer.
 
Optional STP Link support
 
Configurable as initiator/target based on device type
 
All supported primitive sequences (Single/Repeated/Triple/Redundant)
 
Reserved Primitive substitution
 
Idle generator (scrambled data words
 
Replace ALIGN with NOTIFY on request or randomize
 
Configurable/randomized ALIGN type sent
 
Elasticity Buffer
 
Configurable SAS Address
 
Configurable timeouts
 
Port Layer
 
Any combination of Phys per Wide Port
 
Randomized/iterative selection of PHY
 
Randomized use of multiple simultaneous connections
 
Configurable connection close policies
 
PHY Layer Features
 
SERDES model with digital receiver clock recovery
 
OOB sequence generation and checking
 
Speed negotiation - SNW-1,2 and SNW-3 - 1.5 to 6Gb
 
Support for Phy Multiplexing
 
Configurable Spread Spectrum Clocking (SSC) generation
 
Kcode and Dcode Checking
 
8b/10b Encode and Decode functions with disparity checking
 
Controls to inject bit errors
 
Controls for Dword/Primitive override
 
Configurable timeouts
 
Please contact us for an in-depth product brief
 
 
Phone: 805-428-0839 • Email: info@expertio.com
Copyright 2003-2007, Expert IO