Sample

PCI Express (PCIe) Verification IP

The PCI Express (PCIe) System Verification Component (SVC) is designed to help you thoroughly verify your design using both random and directed simulation. The PCIe SVC supports constrained randomization parameters throughout the layers to aid in coverage during testing.

The SVC is implemented to be verification methodology neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog).

Overall Features
  • Root Complex and Endpoint models
  • Optional switch model
  • Support separate for host and target memories
  • Selection of PIPE, PCS/PMA level, or SERDES interfaces
  • Support for Gen 1, 2 and 3, including SSC
  • Full link speed and width negotiation up to 32 Lanes
  • User interfaces for capturing sent and received packets for external scoreboard use
  • Automated Error Injections at all layers
  • Scalable for multiple instantiations in a test bench for testing multi-port hosts or devices
  • Checkers verify protocol timing checks and functional accuracy at each layer
  • Configurable pattern generation for random, directed or erroneous patterns
  • A variety of constrained randomized parameters to aid in coverage during randomized testing
  • Statistics reported at each level to help determine
    • corner case coverage
  • User call-backs and hooks for use in directed tests
Application Layer Features
  • Target application supports all transaction types
  • Target application randomizes read completions and ordering
  • Requestor application for automated testing of root and endpoint memory transactions
  • Driver application for easy user transaction level interface
  • Driver handles queuing, completions, and TLP checking for the user
Transaction Layer
  • Queuing for 8 VCs with configurable depth
  • Configurable TC to VC queue mapping
  • Support for multiple Requestor / Completer applications, including user supplied applications
  • User interface for direct TLP queuing and receipt
  • Checks all TLPs for correct formation of headers, prefixes, and ECRC
Data Link Layer Features
  • Full DL state machines
  • Checks all framing, LCRC, and lane rules
  • Check all DLLP fields and formatting
  • Randomization of credit return per VC
  • Randomization of ACK/NAK latency and aggregation
  • Interface to send / receive user defined DLLPs
  • Supports ASPM and Software controlled Power Management
  • Automated Error Injections and checking
PHY Layer Features
  • Full LTSSM state machine
  • SERDES model with digital clock recovery
  • Speed and Link Width negotiation
  • Supports Upconfigure, polarity inversion, and lane-to-lane skew
  • Power Management
  • Configurable Spread Spectrum Clocking (SSC)
  • Gen 1 & 2 PCS, 8b/10b encoding
  • Gen 3 128/130 encoding
  • Configurable timers and timeouts
Compliance Test Suites (optional)
  • Tests verify all aspects of the specifications,
    including:
    • TLP formation and handling rules
    • Retry buffer management
    • LTSSM state transitions and power management
  • Self contained testbench is written in SystemVerilog and is user extendable
  • Includes a complete test plan for your device type

Please contact us for an in-depth product brief