Fibre Channel (FC) Verification IP
The Fibre Channel System Verification Component (SVC) is designed to help you thoroughly verify your ASIC / FPGA design using both random and directed simulation. Constrained randomization parameters exist throughout the layers to aid in coverage during randomized testing. The SVC is environment language neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog).
 
Created by recognized Fibre Channel experts involved with FC since 1992.
 
Overall Features:
 
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 Full Initiator and Target models
 
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 Supports L, N, and F ports
 
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 Supports any speed, including 8Gb. 10Gb XAUI option available.
 
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 SAM-3 Application level exerciser for both unit and system level testing.
 
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 Scalable for multiple instantiations in a test bench (for testing multi-port hosts or devices)
 
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 Checkers will verify protocol timing checks and functional accuracy at each layer.
 
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 Configurable pattern generation for random, directed or erroneous patterns
 
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 A variety of constrained randomized parameters to aid in coverage during randomized testing
 
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 Statistics reported at each level to help determine corner case coverage.
 
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 Callbacks and hooks for use in directed test writing
 
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 Includes the following transactor interfaces for directed testing:
   
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 10 or 20 bit Phy interfaces
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 8 bit Encoder / Decoder interface
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 32 bit Dword Primitive interface
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 Dword level transport interface
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 Complete Frame transaction level interface
 
FCP (SCSI) Exerciser Applications
 
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 Compliant to SCSI Architecture Model 3 (SAM-3)
 
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 Supports multi LUN addressing
 
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 Comprehensive suite of SVC settings that define the behavior and parameters of the commands/task management functions executed by the initiator.
 
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 Host Model Capabilities:
   
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 A single Initiator can communicate with multiple Targets.
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 Initiator can discover target information or have this step skipped and set with appropriate target information
 
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 Target Model Capabilities:
   
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 Target implements a block mode device
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 Target is multiple LUN capable
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 Capable of responding to discovery commands such as INQUIRY, REPORT_LUNS, etc
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 Supports several queuing attribute models
 
Transport Layer: (FC-2, FC-4):
 
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 Frame Level error detection (e.g. CRC, Destination ID, etc)
 
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 Support Port Login and Process Login
 
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 Extended Link Services stimulus/response engine
 
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 Frame Level Statistics
 
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 FC-FS, FC-PH compliant framing generation and checking
 
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 Adaptable to multiple FC-4 Applications
   
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 SCSI over Fibre Channel (FCP-3 Compliant)
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 FCP Statistics
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 SAM-3 standard SCSI Interface
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 Supports multiple outstanding IOs/exchanges
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 Randomization of sequence behavior stressing common pitfalls in FCP
 
Link Layer Features (FC-1, FC-AL)
 
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 Configurable to operate as N Port or L Port
 
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 Ordered Set Sequence Validation
 
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 Elasticity Buffer
 
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 FC-1
   
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 Compliant to FC-PH, FC-FS-2
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 Disparity Checking
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 Kcode and Dcode Checking
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 8b/10b Encode and Decode functions
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 Controls to inject bit errors
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 Controls for Dword/Primitive override
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 FC Port State Machine
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 Nport Statistics (e.g. interframe gap, Simultaneous Rx/Tx traffic detection, etc)
 
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 FC-AL
   
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 Compliant FC-AL2 State Machine
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 Configurable parameters to vary loop behavior
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 Complete Loop Initialization stimulus/response (LIM selection, LIFA, LIPA, LIHA, LISA, LIRP, LILP handling)
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 Lport Statistics (e.g. Duplex detection, Loop tenancy behaviors)
 
Please contact us for an in-depth product brief
 
 
Phone: 805-428-0839 • Email: info@expertio.com
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