Fibre Channel (FC) Verification IP
The Fibre Channel System Verification Component (SVC) is designed to help you thoroughly verify your ASIC / FPGA design using both random and directed simulation. Constrained randomization parameters exist throughout the layers to aid in coverage during randomized testing. The SVC is environment language neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog).
 
Created by recognized Fibre Channel experts involved with FC since 1992.
 
Overall Features:
 
Full Initiator and Target models
 
Supports L, N, and F ports
 
Supports any speed, including 8Gb. 10Gb XAUI option available.
 
SAM-3 Application level exerciser for both unit and system level testing.
 
Scalable for multiple instantiations in a test bench (for testing multi-port hosts or devices)
 
Checkers will verify protocol timing checks and functional accuracy at each layer.
 
Configurable pattern generation for random, directed or erroneous patterns
 
A variety of constrained randomized parameters to aid in coverage during randomized testing
 
Statistics reported at each level to help determine corner case coverage.
 
Callbacks and hooks for use in directed test writing
 
Includes the following transactor interfaces for directed testing:
   
10 or 20 bit Phy interfaces
8 bit Encoder / Decoder interface
32 bit Dword Primitive interface
Dword level transport interface
Complete Frame transaction level interface
 
FCP (SCSI) Exerciser Applications
 
Compliant to SCSI Architecture Model 3 (SAM-3)
 
Supports multi LUN addressing
 
Comprehensive suite of SVC settings that define the behavior and parameters of the commands/task management functions executed by the initiator.
 
Host Model Capabilities:
   
A single Initiator can communicate with multiple Targets.
Initiator can discover target information or have this step skipped and set with appropriate target information
 
Target Model Capabilities:
   
Target implements a block mode device
Target is multiple LUN capable
Capable of responding to discovery commands such as INQUIRY, REPORT_LUNS, etc
Supports several queuing attribute models
 
Transport Layer: (FC-2, FC-4):
 
Frame Level error detection (e.g. CRC, Destination ID, etc)
 
Support Port Login and Process Login
 
Extended Link Services stimulus/response engine
 
Frame Level Statistics
 
FC-FS, FC-PH compliant framing generation and checking
 
Adaptable to multiple FC-4 Applications
   
SCSI over Fibre Channel (FCP-3 Compliant)
FCP Statistics
SAM-3 standard SCSI Interface
Supports multiple outstanding IOs/exchanges
Randomization of sequence behavior stressing common pitfalls in FCP
 
Link Layer Features (FC-1, FC-AL)
 
Configurable to operate as N Port or L Port
 
Ordered Set Sequence Validation
 
Elasticity Buffer
 
FC-1
   
Compliant to FC-PH, FC-FS-2
Disparity Checking
Kcode and Dcode Checking
8b/10b Encode and Decode functions
Controls to inject bit errors
Controls for Dword/Primitive override
FC Port State Machine
Nport Statistics (e.g. interframe gap, Simultaneous Rx/Tx traffic detection, etc)
 
FC-AL
   
Compliant FC-AL2 State Machine
Configurable parameters to vary loop behavior
Complete Loop Initialization stimulus/response (LIM selection, LIFA, LIPA, LIHA, LISA, LIRP, LILP handling)
Lport Statistics (e.g. Duplex detection, Loop tenancy behaviors)
 
Please contact us for an in-depth product brief
 
 
Phone: 805-428-0839 • Email: info@expertio.com
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