Sample

Ethernet Verification IP

The Ethernet Verification IP includes an Ethernet Packet generator, packet checking scoreboard, MAC and Reconsilation Sublayer transactor components. A selection of Phy layer components are available, including 10/100/1000Mb, XAUI/XFI (10Gb), KX, KX4, KR, and 40/100Gb PCS). The model implements constrained randomization parameters throughout to aid in coverage during testing. The SVC is implemented to be environment language neutral, and can be integrated with and controlled by any HVL (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog). The usage of the model is very OVM like.

The Ethernet System Verification Component (SVC) is designed to help you thoroughly verify your design using both random and directed simulation. With these tools, one can test a variety of DUTs including switches, routers, Network Interface Cards (NICs) and Phys.

Overall Features
  • Compliant with 802.3 specifications and industry practices
  • The MAC and RS port model supports MII, GMII, XGMII, XLGMII and variations
  • Can be used at any speed from 10Mb up to 40/100Gb
  • Auto Negotiation support.
  • Port model (MAC and RS) can be used with or without a Phy Layer
  • Constrained Packet Generator creates varying types of destination addresses, Q tags, and size
  • Packet checker Scoreboard compares sent and received packets, including errored packets.
  • A variety of Phy Layers can be added for 10/100/1000Gb, XAUI, XFI, KX, KX4, KR, 40/100G and others
  • Scalable for multiple instantiations in a test bench (for testing multi-port hosts or devices)
  • Checkers will verify protocol timing checks and functional accuracy at each layer.
  • Configurable pattern generation for random, directed or erroneous patterns
  • A variety of constrained randomized parameters to aid in coverage during randomized testing
  • Statistics reported at each level to help determine corner case coverage.
Ethernet Packet Generator
  • Generation based on either Built in Bandwidth Rate Limiter or randomized delay
  • Ethernet or 802.3 mode
  • Supports multiple address pair flows, Multicast, Broadcast
  • Multiple VLs and 802.1Q priority mapping / generation
  • VL Pause support (avoids head of line blocking)
  • All generation constraints can be changed per packet on the fly.
Packet Checking Scoreboard
  • Checks against both expected good and expected bad packets queues.
  • Can be configured to handle differing expected DUT error behaviours.
  • Side by side packet comparison display
MAC and RS port model
  • Generation and checking of the Inter-Packet Gap, Preamble, SFD, and EFD
  • Supports MII, GMII, XGMII, XLGMII and other interfaces to DUT or optional Phy Layers
  • Interface tasks to Packet Generator and Checker Scoreboard
  • VL Pause generation / checking
  • Built in Error Injection for Packet errors, IPG, Preamble, CRC, etc
  • Statistics on packets, gaps, errors, etc
Optional PHY Layer Features
  • SERDES model with digital receiver clock recovery
  • Interfaces to technology appropriate bus (ie XGMII, GMII, MII
  • Technologies Available: 10/100/1000 Base T, KX, XAUI, XFI, KX4, KR, 40/100Gb
  • Technology dependant Encode function and Decode Checking
  • Controls to inject disparity, bit flip, and encoding errors

Please contact us for an in-depth product brief